diff --git a/src/libvm/src/interrupt.rs b/src/libvm/src/interrupt.rs
index 0f6f004..848dfd4 100644
--- a/src/libvm/src/interrupt.rs
+++ b/src/libvm/src/interrupt.rs
@@ -14,10 +14,16 @@ macro_rules! interrupts {
 }
 
 interrupts! {
-    DIVIDE_BY_ZERO = 0,
-    INVALID_OPCODE = 1,
-    ILLEGAL_MEMORY_ADDRESS = 2,
-    HARDWARE_EVENT = 3,
+    // Error state exceptions
+
+    DOUBLE_FAULT           = 0x00,
+    INVALID_OPCODE         = 0x01,
+    ILLEGAL_MEMORY_ADDRESS = 0x02,
+    DIVIDE_BY_ZERO         = 0x03,
+
+    // General exceptions
+    
+    //IO_EVENT               = 0x80,
 }
 
 pub const IVT_LENGTH: usize = 512;
diff --git a/vm.md b/vm.md
index 34d3db8..e61a68b 100644
--- a/vm.md
+++ b/vm.md
@@ -322,34 +322,50 @@ the above actions occur in reverse:
 
 ## Exceptions
 
-The first 256 interrupt vectors are reserved for CPU and hardware-sourced events - these are known
-as exceptions. Exceptions may occur for a number of reasons:
+The first 256 interrupt vectors are reserved for CPU and I/O-sourced events - these are known as
+exceptions. Likewise, the first 128 exceptions are error state exceptions, with the remaining 128
+being used for general exceptions.
 
-* Illegal operation attempted, e.g. divide by zero or accessing protected memory
-* Illegal operation attempted while handling an interrupt (double fault)
-* A hardware event occurred, e.g. a timer tick
+### Error state exceptions
 
-The following list defines all exceptions that the CPU may invoke. All other vectors in 0-255 not
-defined in this table are reserved and may be used in the future.
+Error state exceptions occur when an instruction attempts to perform illegal operation,
+such as attempting to read an out-of-bounds memory address or attempting to execute an invalid
+opcode. Error state exceptions may be caught and handled, just like any other interrupt.
 
-* Divide by zero
-    * Interrupt vector: 0
-    * Auxiliary: N/A
-    * Invoked upon a divide-by-zero
+#### Double fault and triple fault
+
+If, while already handling an error state exception, and a second error state exception is raised, a
+double fault is invoked. You may handle a double fault like any exception and attempt to repair the
+situation. If yet another exception is raised, the CPU will invoke a triple fault. A triple fault
+will unconditionally halt the machine.
+
+### Error state exceptions (vectors 0x00-0x0f)
+
+* Double fault
+    * Interrupt vector: 0x00
+    * Auxiliary: 
+    * An error state interrupt occurred while already handling an error state interrupt
 * Invalid opcode
-    * Interrupt vector: 1
+    * Interrupt vector: 0x01
     * Auxiliary: N/A
     * Attempted to invoke an illegal opcode
 * Illegal memory address
-    * Interrupt vector: 2
+    * Interrupt vector: 0x02
     * Auxiliary: Memory address causing the interrupt
     * Attempted to access a memory address in an illegal way - either it's out of bounds or is
       protected in some way.
-* Hardware event
-    * Interrupt vector: 3
-    * Auxiliary: Pointer to the hardware event structure.
-    * A hardware device has an event that needs attention.
-* Interrupt vector 4-255: Reserved for future use
+* Divide by zero
+    * Interrupt vector: 0x03
+    * Auxiliary: N/A
+    * Invoked upon a divide-by-zero
+* Remaining error states below 0x80 are reserved for future use.
+
+### General exceptions (vectors 0x80-0xff)
+* I/O event
+    * Interrupt vector: 0x80
+    * Auxiliary: Pointer to the I/O event structure.
+    * An I/O device has an event that needs attention.
+    * NOTE: This will probably be removed.
 
 # Binary object format