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Add/rename/implement instructions based on new spec

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* Add Mod instruction
* Rename Neg -> INeg
* Rename Copy -> MemCopy
* Add RegCopy

Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
This commit is contained in:
Alek Ratzloff
2020-01-26 11:18:53 -05:00
parent ce0ab273f0
commit f95c24ee95
2 changed files with 11 additions and 4 deletions
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6
src/vm/inst.rs
View File

@@ -6,7 +6,8 @@ pub enum Inst {
Add(Reg, Reg),
Mul(Reg, Reg),
Div(Reg, Reg),
Neg(Reg),
Mod(Reg, Reg),
INeg(Reg),
And(Reg, Reg),
Or(Reg, Reg),
Xor(Reg, Reg),
@@ -21,7 +22,8 @@ pub enum Inst {
Load(Reg, Reg),
Store(Reg, Reg),
StoreImm(Reg, u32),
Copy(Reg, Reg),
MemCopy(Reg, Reg),
RegCopy(Reg, Reg),
Nop,
Halt,

9
src/vm/vm.rs
View File

@@ -164,7 +164,8 @@ impl Vm {
self.set_reg(r1, value);
}
Inst::Div(r1, r2) => map!(r1 = r1 / r2),
Inst::Neg(r1) => {
Inst::Mod(r1, r2) => map!(r1 = r1 % r2),
Inst::INeg(r1) => {
let value = self.get_reg(r1);
let ivalue = -i64::from_ne_bytes(value.to_ne_bytes());
let uvalue = u64::from_ne_bytes(ivalue.to_ne_bytes());
@@ -212,7 +213,11 @@ impl Vm {
Inst::StoreImm(r1, value) => {
self.set_reg(r1, value as u64);
}
Inst::Copy(r1, r2) => {
Inst::RegCopy(r1, r2) => {
let w1 = self.get_reg(r2);
self.set_reg(r1, w1);
}
Inst::MemCopy(r1, r2) => {
let w1 = self.load(r2);
self.store(r1, w1);
}