Commit Graph

16 Commits

Author SHA1 Message Date
2c4b56e362 Use lrpar for parsing, big 'ol syntax overhaul
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-02-17 16:15:06 -05:00
e198da5825 Finish up parser and assembler with more-or-less complete syntax
Major changes inlude:

* Bit the bullet and now instructions have their length hard-coded
* Move from_utf8 object parsing to be done by their objects (instead of
  a Parser god object)
* A list of AST sections are assembled into an Object using the new
  vm::obj::assemble module.
* Changed the object layout some in the spec, and adjusted code to match
  this.

Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-02-09 13:04:56 -05:00
329e61e087 Fix typos in some of the opcode binary layouts
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-02-03 18:00:24 -05:00
47ee61ca0d Finish up the opcode ascii table layouts
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-28 19:27:25 -05:00
2148fed5a5 Add opcodes and layout for most instructions
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-28 19:16:52 -05:00
785c0c6092 Update phrasing of 'Bin' and 'format' to 'object'
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-28 18:35:41 -05:00
25f89bbc73 Initial binary object layout spec and matching impl (sans code)
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-28 18:35:41 -05:00
a5388c8b86 Add more great ideas to the VM spec
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-28 18:35:41 -05:00
a5bd09d7d6 Add Not and Inv instructions to spec
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-28 18:27:19 -05:00
ce0ab273f0 Add "miscellaneous" instructions section, move Halt to there, add Nop
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-26 11:17:21 -05:00
c8690e79bc Add more notes, some other TODOs, STATUS register
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-26 11:15:09 -05:00
6c96adddff Add a few notes about numbers and arithmetic, rename Neg -> INeg
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-26 10:59:25 -05:00
df950c6f63 Fix arithmetic instruction specs
Originally, arithmetic instructions were in the form of

    REG2 = REG1 (OP) REG2

but then I started storing the result in REG1 (both in implementation,
and later defs of the arth instructions). So I'm updating it to match
what was actually in my head.

Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-26 10:52:26 -05:00
Max Marrone
976b0689ba Add a modulo instruction. 2020-01-25 21:06:43 -05:00
Max Marrone
b7aa2d7ce7 Rename Copy to MemCopy and also add RegCopy. 2020-01-25 21:02:32 -05:00
ddfcec0427 Initial commit
Signed-off-by: Alek Ratzloff <alekratz@gmail.com>
2020-01-25 19:17:39 -05:00