329e61e087
Fix typos in some of the opcode binary layouts
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-02-03 18:00:24 -05:00
214f0b8aed
Add object layout, object parsing, instruction layout
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* Object layout and parsing are done in the vm::obj module
* Add MemCursor, a wrapper around the std::io::Cursor type for walking
through VM memory
* Add vm::tick module for containing the Vm::tick() method
implementation, since it's pretty big
* Instructions are now variable-sized, and are read lazily,
one-at-a-time directly from memory.
* Add VM runtime error structure
* Probably some other stuff I forgot
Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-02-03 17:56:32 -05:00
47ee61ca0d
Finish up the opcode ascii table layouts
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 19:27:25 -05:00
e8b874a3c9
Implement ObjParser::parse_sections
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 19:17:35 -05:00
2148fed5a5
Add opcodes and layout for most instructions
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 19:16:52 -05:00
54f61101c6
Rename vm::bin -> vm::obj
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
785c0c6092
Update phrasing of 'Bin' and 'format' to 'object'
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
25f89bbc73
Initial binary object layout spec and matching impl (sans code)
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
f98a53654e
Update/add instructions in parser
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* StoreImm just uses a u64 instead of u32 - we'll figure out the layout
later
* Jmp implementation added (can't believe I forgot this)
* Add Inst AST item, whose immediates don't have to be a u64 right away
Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
7e6c621c2b
Update test.asm to conform to newest syntax
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
c4c196a136
Add lexer dump to main and fix a couple of bugs
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
a5388c8b86
Add more great ideas to the VM spec
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
b16974c7c4
Update registers to be constants, add instructions to parser
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
abf32665e2
Add allow(dead_code) to span
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
ae32403d1f
Remove syn::vm::pass
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:35:41 -05:00
a5bd09d7d6
Add Not and Inv instructions to spec
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-28 18:27:19 -05:00
f95c24ee95
Add/rename/implement instructions based on new spec
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* Add Mod instruction
* Rename Neg -> INeg
* Rename Copy -> MemCopy
* Add RegCopy
Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-26 11:18:53 -05:00
ce0ab273f0
Add "miscellaneous" instructions section, move Halt to there, add Nop
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-26 11:17:21 -05:00
c8690e79bc
Add more notes, some other TODOs, STATUS register
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-26 11:15:09 -05:00
6c96adddff
Add a few notes about numbers and arithmetic, rename Neg -> INeg
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-26 10:59:25 -05:00
df950c6f63
Fix arithmetic instruction specs
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Originally, arithmetic instructions were in the form of
REG2 = REG1 (OP) REG2
but then I started storing the result in REG1 (both in implementation,
and later defs of the arth instructions). So I'm updating it to match
what was actually in my head.
Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-26 10:52:26 -05:00
Max Marrone
976b0689ba
Add a modulo instruction.
2020-01-25 21:06:43 -05:00
Max Marrone
b7aa2d7ce7
Rename Copy to MemCopy and also add RegCopy.
2020-01-25 21:02:32 -05:00
ddfcec0427
Initial commit
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Signed-off-by: Alek Ratzloff <alekratz@gmail.com >
2020-01-25 19:17:39 -05:00
